1. Field of the Invention
The present invention generally relates to a synchronizing pattern position detection circuit that detects the position of a synchronizing pattern on parallel data obtained by a serial-to-parallel conversion of serial data transmitted in a frame unit.
Serial data transmitted on the frame basis may be converted into parallel data having a given bit width. If the serial-to-parallel conversion does not make reference to the head of the frame, it is required to detect, on parallel data, the position of a synchronizing pattern located in the head of the frame in order to know the position of the beginning bit of the frame on the parallel data.
2. Description of the Related Art
A conventional synchronizing pattern position detection circuit equipped with a priority encode circuit is known. The priority encode circuit masks a synchronizing pattern detection signal having priority lower than that of another synchronizing pattern detection signal indicative of a synchronizing pattern detection value.
The above priority encode circuit needs a plurality of stages of gate circuits as many as the bits of parallel data in order to mask the synchronizing pattern detection signal having priority lower than that of the synchronizing pattern indicating the synchronizing pattern detection circuit. This would result in an increased delay of time, which would prevent high-speed detection of the target synchronizing pattern on the parallel data.